điện tử số Digital Electronic

Digital Electronics
Dr. Pham Ngoc Nam
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Acknowledgement
The main part of the slides was adopted and modified from the original slides of Prof. Rudy Lauwereins, Vice president of IMEC, Leuven, Belgium with his permission.

Your instructor
Bộ môn kỹ thuật điện tử tin học
Office: C9-401
Email: [email protected]
Research:
FPGA, PSoC, hệ nhúng
Trí tuệ nhân tạo
Education:
K37 điện tử-ĐHBK Hà nội (1997)
Master về trí tuệ nhân tạo 1999, Đại học K.U. Leuven, vương quốc Bỉ
Đề tài: Nhận dạng chữ viết tay
Tiến sỹ kỹ thuật chuyên ngành điện tử-tin học, 9/ 2004, Đại học K.U. Leuven-IMEC, Vương Quốc Bỉ
Đề tài: quản lý chất lượng dịch vụ trong các ứng dụng đa phương tiện tiên tiến

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Course contents
Digital design
Combinatorial circuits: without status
Sequential circuits: with status
FSMD design: hardwired processors
Language based HW design: VHDL

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Course contents
Digital design
Combinatorial circuits: without status
Sequential circuits: with status
FSMD design: hardwired processors
Language based HW design: VHDL
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
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Contents of “Digital Design”
Introduction to the course
Course book
Goal
Exercises and laboratory sessions
Exam
Data representation
Boolean algebra
Logical gates
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Contents of “Digital Design”
Introduction to the course
Course book
Goal
Exercises and laboratory sessions
Exam
Data representation
Boolean algebra
Logical gates
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Course books
Mandatory:
“Principles of Digital Design”, Daniel D. Gajski, Prentice Hall, 1997, ISBN 0-13-301144-5
References:
Douglas L. Perry, VHDL: Programming by Examples, McGraw-Hill, fourth Edition, 2002.
“Logic and Computer Design Fundamentals”, M. Morris Mano & Charles R. Kime, Prentice Hall, 2nd edition, 2000, ISBN 0-13-016176-4
TS. Nguyễn Nam Quân : “Toán logic và Kỹ thuật số”, Nhà xuất bản khoa học và kỹ thuật, 2006
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Contents of “Digital Design”
Introduction to the course
Course book
Goal
Exercises and laboratory sessions
Exam
Data representation
Boolean algebra
Logical gates
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Goal of the course
Give insight in the design of digital electronic systems at the gate and register-transfer level
Teach the use of modern design tools
Offer all building blocks needed to construct complex digital circuits, including processors
Present the difference between functional requirements (operation) and non-functional requirements (cost, speed, power, area)
Introduce modern implementation platforms: PLA, PLD, FPGA
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Contents of “Digital Design”
Introduction to the course
Course book
Goal
Exercises and laboratory sessions
Exam
Data representation
Boolean algebra
Logical gates
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Exercises and laboratory sessions
Bài 1: Các phần tử logic cơ bản – Bộ chọn dữ liệu phân kênh
Bài 2: Các Trigơ RS, D, JK – Bộ đếm LED 7 thanh
Bài 3: Làm quen với phần mềm thí nghiệm thông qua một ví dụ thiết kế đơn giản
Bài 4: Thiết kế bộ so sánh hai số 3 bit: Bài thí nghiệm này giúp sinh viên luyện tập tối thiểu hóa bìa Karnaugh 6 biến và biết cách thiết kế mạch logic tổ hợp từ các phần tử logic cơ bản
Bài 5: Thiết kế bộ phát hiện tổ hợp bit trong một chuỗi bit: Giúp sinh viên biết cách xây dựng máy trạng thái và thiết kế hệ thông số bằng máy trạng thái
Bài 6: Thực hiện thuật toán FIR dùng cấu trúc FSMD
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Contents of “Digital Design”
Introduction to the course
Course book
Goal
Exercises and laboratory sessions
Exam
Data representation
Boolean algebra
Logical gates
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Exam
Close book
Midterm exam: 30%
Final exam: 70%
Completing lab sessions is a must before taking the exam

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Contents of “Digital Design”
Introduction to the course
Data representation
Decimal, Binary, Octal, Hexadecimal
Addition, subtraction, multiplication, division
Negative numbers
Integer, fixed point, fractional, floating point, BCD, ASCII
Boolean algebra
Logical gates
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Contents of “Digital Design”
Introduction to the course
Data representation
Decimal, Binary, Octal, Hexadecimal
Addition, subtraction, multiplication, division
Negative numbers
Integer, fixed point, fractional, floating point, BCD, ASCII
Boolean algebra
Logical gates
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Decimal
1234.56710=
1•1000+2•100+3•10+4•1+5•0.1+6•0.01+7•0.001
1•103+2•102+3•101+4•100+5•10-1+6•10-2+7•10-3
r = radix (r = 10), d=digit (0  d  9), m = #digits before radix point (decimal point), n = #digits after decimal point
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Binary
1011.0112=
1•8+0•4+1•2+1•1+0•0.5+1•0.25+1•0.125
1•23+0•22+1•21+1•20+0•2-1+1•2-2+1•2-3
r = radix (r = 2), d = digit (0  d  1), m = #digits before radix point (binary point), n = #digits after radix point
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Octal
7654.328=
7•512+6•64+5•8+4•1+3•0.125+2•0.015625
7•83+6•82+5•81+4•80+3•8-1+2•8-2
r = radix (r = 8), d = digit (0  d  7), m = #digits before radix point (octal point), n = #digits after radix point
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Hexadecimal
FEDC.7616=
15•4096+14•256+13•16+12•1+7•1/16+6•1/256
15•163+14•162+13•161+12•160+7•16-1+6•16-2
r = radix (r = 16), d = digit (0  d  F), m = #digits before radix point (hexadecimal point), n = #digits after radix point
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Contents of “Digital Design”
Introduction to the course
Data representation
Decimal, Binary, Octal, Hexadecimal
Addition, subtraction, multiplication, division
Negative numbers
Integer, fixed point, fractional, floating point, BCD, ASCII
Boolean algebra
Logical gates
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Binary addition
Binary addition
Decimal addition
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Binary subtraction
x
y
borrow
result
1 1 1 0 1
1 1 1 1
1 1 1 0
0 1 1 1 0
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Binary multiplication
1 1 1 0
1 1 0 1
1 1 1 0
0 0 0 0
1 1 1 0
1 1 1 0
1 0 1 1 0 1 1 0
Multiplication by repeated add & shift: number of cycles = number of bits of multiplier
Can be implemented in a faster way
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Binary division
1 0 1 1 1 0 1 0
0 0 0 0
1 1 1 0
1 0 0 1 0 1 0
1 1 1 0
1 0 0 1 0
1 1 1 0
1 0 0 1 0
1 1 1 0
1 0 0
1 1 0 1
Division by repeated subtract & shift: number of cycles = number of bits of result
Mostly done this way
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Contents of “Digital Design”
Introduction to the course
Data representation
Decimal, Binary, Octal, Hexadecimal
Addition, subtraction, multiplication, division
Negative numbers
Integer, fixed point, fractional, floating point, BCD, ASCII
Boolean algebra
Logical gates
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Sign-Magnitude representation
Each number consists of two parts : sign and magnitude
Decimal example: +12310 (by convention also ‘123’) and -12310
Binary: sign represented by MSB; ‘0’ = positive, ‘1’ = negative
Binary example: 011002 = +1210 en 111002 = -1210
A sign-magnitude integer with n bits lies between -(2n-1-1) and +(2n-1-1) with two representations for 0: 000...0 en 100...0
Generic representation of a sign-magnitude integer: B =
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Sign-Magnitude addition and subtraction
Start
addition
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Sign-Magnitude addition and subtraction
Multiplication and division are repeated add/subtract & shift and can hence be carried out with such an adder/subtractor
Sign-magnitude representation leads to slow, expensive adder/subtractor due to repeated comparison and test of sign and magnitude
This is why we represent numbers mostly using two’s complement notation
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Two’s complement notation
Radix-complement of a number D with m digits is D* = rm - D
eg. The 10-complement of 12310 is
103 - 12310 = 87710
eg. The 2-complement of 11012 is
24 - 1310 = 310 = 00112
Call D’ the digit complement, then D*=D’+1 (proof in book); this offers us an easier way of determining the two’s complement:
eg. The 2-complement of 11012 is
00102 + 00012 = 00112
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Two’s complement notation
How do we negate a number D, i.o.w. how do we obtain -D?
D* = rm - D  D* + D = rm = 0 when we retain only the m least significant digits 
D* = -D
eg. D=00112  D*=11002+00012=11012
D+D*=00112+11012=100002=24=0 when we retain only the m least significant bits; we may hence use D*=11012 for the binary representation of -D=-310
What is the negation of D=00002? D*=11112+00012=100002=00002
There is only 1 notation for ‘zero’
A 2-complement integer with n bits lies between -(2n-1) and +(2n-1-1)

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Two’s complement notation
Negating a 2-complement number requires many more
bit-flips than negating a sign-magnitude number:
sign-magnitude is less power hungry than 2-complement
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Two’s complement addition and subtraction
The negation needed for the subtraction is done by taking the bit-complement of B2; the addition of the ‘1’ is done by putting the LSB carry-in of the next addition to 1.
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Two’s complement addition and subtraction
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Contents of “Digital Design”
Introduction to the course
Data representation
Decimal, Binary, Octal, Hexadecimal
Addition, subtraction, multiplication, division
Negative numbers
Integer, fixed point, fractional, floating point, BCD, ASCII
Boolean algebra
Logical gates
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Integer, fixed point, fractional, floating point
Integer
int: 101011.  m=6
int+int = int and mmax(m1,m2)+1
int•int = int and m=m1+m2
Fixed point
fix: 1101.010  i = 4, f = 3
fix+fix = fix and imax(i1,i2)+1 & fmax(f1,f2)
fix(i1,f1)•fix(i2,f2) = fix and i=i1+i2 & f=f1+f2

mm1+log216
m=16•m1
ii1+log216 &
f=f1
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Integer, fixed point, fractional, floating point
Fractional
frac: 0.01101  f = 5
frac+frac = fix<1,f> and fmax(f1,f2)
frac•frac = frac and f=f1+f2
Floating point
float: 0.11010•2^101  m = 5, e = 3

ilog216 &
f=f1
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BCD
Binary Coded Decimal number
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ASCII
American Standard Code for Information Interchange (7-bit code)
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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Axiomatic definition of Boolean algebra
A1 (Closure):
B is closed w.r.t. + (OR)
B is closed w.r.t. • (AND)
A2 (Identity element)
B has an identity element w.r.t. +, designated by 0
B has an identity element w.r.t. •, designated by 1
A3 (Commutativity)
B is commutative w.r.t. +, i.o.w. x+y=y+x
B is commutative w.r.t. •, i.o.w. x•y=y•x

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Axiomatic definition of Boolean algebra
A4 (Distributivity)
• is distributive w.r.t. +, i.o.w. x•(y+z)=(x•y)+(x•z)
+ is distributive w.r.t. •, i.o.w. x+(y•z)=(x+y)•(x+z)
A5 (Complement element -- NOT operator)
xB, x’B: x+x’=1
xB, x’B: x•x’=0
A6 (Cardinality bound)
There exist at least two different elements in B
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Axiomatic definition of Boolean algebra
Differences w.r.t. ordinary algebra
In ordinary algebra + is not distributive w.r.t. •:
5+(2•4)  (5+2) • (5+4)
In boolean algebra, an inverse operation for the addition (OR) does not exist, neither for the multiplication (AND); subtraction and division hence do not exist
In ordinary algebra it is not true that x + x’ = 1 and x • x’ = 0
Boolean algebra works with a finite set of elements, whereas ordinary algebra has an infinite set
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Axiomatic definition of Boolean algebra
Two-valued Boolean algebra (defined by Shannon)
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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Theorems of Boolean algebra
Theorem 1: idempotency
x + x = x
x • x = x (Note the duality!!)
Theorem 2
x + 1 = 1
Dual: x • 0 = 0
Theorem 3: absorption
y • x + x = x (priority: • before +)
Dual: (y + x) • x = x
Theorem 4: involution
(x’)’ = x

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Theorems of Boolean algebra
Theorem 5: associativity
(x + y) + z = x + (y + z)
Dual: (xy)z = x(yz)
Theorem 6: De Morgan’s law
(x+y)’ = x’y’
Dual: (xy)’ = x’+y’
Proof: using axioms or truth table
Duality:
Replace each OR by AND and AND by OR
Replace each 0 by 1 and x by x’
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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Boolean functions
What: expression in binary variables and the operators AND, OR, NOT
Priority:
parenthesis
NOT
AND
OR
Eg. F1=xy+xy’z+x’yz
F1=1 when x=1 and y=1 or when x=1, y=0 and z=1 or when x=0, y=1 and z=1; in all other cases F1=0
F1 consists of 3 AND-terms and 1 OR-term
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Boolean functions
Realisation of F1=xy+xy’z+x’yz
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Boolean functions
Truth table for F1=xy+xy’z+x’yz
n variables  2n rows
standard numbering
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Boolean functions
Building up a truth table using standard numbering:
X
Y
Z
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Boolean functions
Truth table for F1=xy+xy’z+x’yz
numbering following the Gray code (two consecutive rows only differ in 1 variable)
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Boolean functions
Building up a truth table using the Gray code:
X
Y
Z
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Boolean functions
Complement of a Boolean function
F1’ =(xy+xy’z+x’yz)’
=(xy)’(xy’z)’(x’yz)’ (De Morgan)
=(x’+y’)(x’+y+z’)(x+y’+z’) (De Morgan)

This gives us the opportunity to convert an AND-OR implementation in an OR-AND implementation (see next slide)
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Boolean functions
Realisation as AND-OR: F1=xy+xy’z+x’yz
Realisation as OR-AND: F1=((x’+y’) (x’+y+z’) (x+y’+z’))’
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Boolean functions
Algebraic manipulation
F1 =xy+xy’z+x’yz =xy+xyz+xy’z+x’yz (absorption)
=xy+x(y+y’)z+x’yz (distributive)
=xy+x1z+x’yz (complement)
=xy+xz+x’yz (identity)
=xy+xyz+xz+x’yz (absorption)
=xy+xz+(x+x’)yz (distributive)
=xy+xz+1yz (complement)
=xy+xz+yz (identity)
This alternative form is cheaper (see next slide)
There does not exist a fixed rule to combine theorems to guarantee a cheaper result
Further slides will present a non-algebraic method that always leads to the cheapest solution
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Boolean functions
F1=xy+xz+yz
F1=xy+xy’z+x’yz
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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Canonical form
How do we translate a truth table into a Boolean expression?
Definition: a minterm is a Boolean function that is true in 1 row of the truth table and false elsewhere
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Canonical form
A 1-minterm is a minterm for which the function equals 1; a 0-minterm is a minterm for which the function equals 0
For F1=xy+xy’z+x’yz
Each Boolean function can be expressed as the sum of its 1-minterms : F1=x’yz+xy’z+xyz’+xyz=m3+m5+m6+m7=(3,5,6,7)
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Canonical form
Dual definition: a maxterm is a Boolean function that is false in 1 row of the truth table and true elsewhere
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Canonical form
A 0-maxterm is a maxterm for which the function equals 0; a 1-maxterm is a maxterm for which the function equals 1
For F1=xy+xy’z+x’yz
Each Boolean function can be expressed as the product of its 0-maxterms:
F1 =(x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
=M0M1M2M4=(0,1,2,4)
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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Standard form -- minimal implementation in two layers
In the canonical form each function is a sum of 1-minterms or a product of 0-maxterms
Each minterm or maxterm contains all variables => expensive implementation
The standard form is a sum of product terms or a product of sum terms with the smallest number of variables
A product term or sum term does not necessarily contain all variables => cheaper implementation
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Standard form -- minimal implementation in two layers
Example 1
F2 =xyz+xyz’+xy’z+xy’z’
=xy(z+z’)+xy’(z+z’)
=xy+xy’
=x(y+y’)
=x
Example 2
F3 =xyz+xyz’+xy’z+x’yz+x’y’z’
=xyz+xyz’+xyz+xy’z+xyz+x’yz+x’y’z’
=xy(z+z’)+x(y+y’)z+(x+x’)yz+x’y’z’
=xy+xz+yz+x’y’z’
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Standard form -- minimal implementation in two layers
The standard form is the cheapest implementation in two layers
Eg. F2=xy+xz+yz
A non-standard form in more than two layers may be cheaper
Eg. F2=x(y+z)+yz
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Axiomatic definition of Boolean algebra
Theorems of Boolean algebra
Boolean functions
Canonical form
Standard form
The 16 functions of 2 variables
Logical gates
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The 16 functions of 2 variables
Why 16 functions?
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The 16 functions of 2 variables
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Implementation technologies
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Switching transistor
Basic logical gates
Gates with multiple inputs (fan-in)
Multiple operators in a single gate
Non-functional properties
Implementation technologies
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Switching transistor
Basic logical gates
Gates with multiple inputs (fan-in)
Multiple operators in a single gate
Non-functional properties
Implementation technologies
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Switching transistor
p
n+
n+
Gate
Source
Drain
Metal
Isolator
n-MOS transistor
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Switching transistor
p
n+
n+
Vss
Vss
Vss
n-MOS transistor
Infinite number
of free electrons
Hardly any
free electrons:
no conducting path
between Source
and Drain
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Switching transistor
p
n+
n+
Vss
Vss
Vss
n-MOS transistor
Vcc
Many free electrons
attracted by positive
gate voltage:
conducting channel
between Source
and Drain
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Switching transistor
p-MOS transistor
Similar construction, but ‘p’ and ‘n’ doping reversed
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Switching transistor
Basic logical gates
Gates with multiple inputs (fan-in)
Multiple operators in a single gate
Non-functional properties
Implementation technologies
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Basic logical gates
Invertor
F=x’, 2 transistors, relative propagation delay: 1
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Basic logical gates
Driver
F=x, 4 transistors, relative propagation-delay: 2; goal: higher power drive
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Basic logical gates
NAND
F=(xy)’, 4 TOR, relative propagation-delay: 1.4
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Basic logical gates
NOR
F=(x+y)’, 4 TOR, relative propagation-delay: 1.4
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Basic logical gates
AND
F=xy, 6 TOR, relative propagation-delay: 2.4
x
F
y
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Basic logical gates
OR
F=x+y, 6 TOR, relative propagation-delay: 2.4
x
F
y
Vcc
Vss
x
y
x
y
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Basic logical gates
XNOR
F=(xy)’, 12 TOR,
relative
propagation-
delay: 3.2
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Basic logical gates
XOR
F=(xy), 12 TOR,
relative
propagation-
delay: 3.2
x
F
y
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Switching transistor
Basic logical gates
Gates with multiple inputs (fan-in)
Multiple operators in a single gate
Non-functional properties
Implementation technologies
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Gates with multiple inputs (fan-in)
3-input NAND
F=(xyz)’, 6 TOR,
relative
propagation-
delay: 1.8
z
F
y
Vcc
Vss
x
y
x
y
F
x
z
z
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Switching transistor
Basic logical gates
Gates with multiple inputs (fan-in)
Multiple operators in a single gate
Non-functional properties
Implementation technologies
1/92
Multiple operators in a single gate
2-wide 2-input
AND-OR-Invert
F=(xy + zw)’, 8 TOR,
relative
propagation-
delay: 2.2
y
Vcc
Vss
x
y
x
y
x
w
z
z
w
z
w
F
F
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Multiple operators in a single gate
2-wide 2-input
OR-AND-Invert
F=((x+y)(z+w))’,
8 TOR,
relative
propagation-
delay: 2.2
y
Vcc
Vss
x
y
x
y
x
w
z
z
w
z
w
F
F
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Logical voltage levels and noise margin
Fan-out
Power dissipation
Propagation delay
Implementation technologies
1/95
Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Logical voltage levels and noise margin
Fan-out
Power dissipation
Propagation delay
Implementation technologies
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Logic voltage levels and noise margin
For CMOS and TTL, 0V corresponds to the logical ‘0’ and 5V to ‘1’ (ideal and in steady state)
Realistically and during transition for TTL invertor:
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Logic voltage levels and noise margin
TTL guarantees a low output level between 0V and 0.4V (=VOL) and recognizes voltages between 0V and 0.8V (=VIL) as logic ‘0’
Noise up to 0.4V peak between output and next input are interpreted correctly
The noise margin is hence VIL-VOL=0.4V
TTL guarantees a high output level between 2.4V (=VOH) and 5V and recognizes voltages between 2.0V (=VIH) and 5V as logic ‘1’
Noise up to 0.4V peak between output and next input are interpreted correctly
The noise margin is hence VOH-VIH=0.4V
1/98
Logic voltage levels and noise margin
Graphical representation of noise margin:
Low
Low
High
High
Vss
Vss
Vcc
Vcc
Output
Input
VOL
VOH
VIL
VIH
Margin
Margin
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Logical voltage levels and noise margin
Fan-out
Power dissipation
Propagation delay
Implementation technologies
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Fan-out: ‘current driven’ technologies cf. TTL, ECL, ...
Fan-out: maximum number of inputs that may be connected to a single output
Depends on the current that may be delivered by the driving gate (source) (IOH) w.r.t. the current consumed by the driven gate (IIH) and on the current sinked by the driving gate (sink) (IOL) w.r.t. the current delivered by the driven gate (IIL)
Fan-out = min(IOH/IIH,IOL/IIL)
IOH
IIH
IOL
IIL
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Fan-out: ‘charge driven’ technologies cf. CMOS
Fan-out: maximum number of inputs that may be connected to a single output
Depends on the current that may be sourced resp. sinked by the driving gate (IOH resp. IOL) w.r.t. the capacity of the connected inputs and the connecting wire and to the switching time allowed
I=dQ/dt=C.dV/dt=C.f.DV => determines maximum switching frequency
e.g. based on realistic values for Xilinx Virtex:
10 pF input capacity, 20 mA drive current, 0.8 pF/cm PCB connect, Vcc=3.3 V
For fan-out=3 and 10 cm PCB connect: C=3*10+0.8*10=38 pF and switching frequency = I/(C.DV)=20 mA/(38 pF * 3.3 V)=160 MHz
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Logical voltage levels and noise margin
Fan-out
Power dissipation
Propagation delay
Implementation technologies
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Power dissipation
TTL dissipates continuously
P=VCC*ICC10mW/gate
1 million gates: 10 KW!!
Only used when high voltages or large currents are needed (busdrivers, …)
CMOS dissipates only while switching
P=C.f.V2 since I=C.f.V
C: proportional to chip area (trend: increase)
f: trend: steep increase: 1MHz  1 GHz
V: trend: steady decrease: 5  3.3  2.5  1.8  1.5  1.2  0.9
Virtex example: P=38 pF*160 MHz*(3.3 V)2=
66 mW per switching pin; assuming 200 pins, half of which switch concurrently, gives 6.6 W for driving the external pins
Advanced microprocessors: 40W  Cooling!!!
Is currently the limiting design factor
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Logical voltage levels and noise margin
Fan-out
Power dissipation
Propagation delay
Implementation technologies
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Propagation delay
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Implementation technologies
SSI, MSI, LSI, VLSI
Custom design, standard cell design
Gate array
PLA, PLD, FPGA
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Implementation technologies
SSI, MSI, LSI, VLSI
Custom design, standard cell design
Gate array
PLA, PLD, FPGA
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SSI, MSI, LSI, VLSI (I)
SSI: Small Scale Integration
< 10 gates per package
gates directly connected to package pins
designed using transistor level design
used using gate level design
MSI: Medium Scale Integration
10 - 100 gates per package
registers, adders, parity generators, …
designed using gate level design
used using RTL design
LSI: Large Scale Integration
100 - 10K gates per package
controllers, data paths
designed using RTL design
used using behavioral level design
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SSI, MSI, LSI, VLSI (II)
VLSI: Very Large Scale Integration
10K - 1M gates per package
memory, microprocessor, microcontroller, FFT
designed using behavioral level design
used using system level design
ULSI: Ultra Large Scale Integration???
1M - ?? Gates per package
2 controllers, 20 DSP processors, 16 Mbyte memory, 10 accelerators, 1 Mgate FPGA, Analog interface, RF
designed using system level design
only one chip needed for complete application ??
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Implementation technologies
SSI, MSI, LSI, VLSI
Custom design, standard cell design
Gate array
PLA, PLD, FPGA
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Custom design
Each transistor and each connection is designed individually as a set of rectangles.
Excellent for optimal design of library elements that are re-used multiple times
Companies design and sell such optimized libraries
Has to be completely re-done each time technology changes (every 18 months!)
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Standard cell design
Library of standard cells
each cell is a gate
standard height, variable width, interleaved by routing channels
all inputs at the top, all outputs at the bottom
Faster design of more complex building blocks
Silicon foundries design and sell such optimized libraries for their processing technology
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Standard cell design
Design Flow
Design entry
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Implementation technologies
SSI, MSI, LSI, VLSI
Custom design, standard cell design
Gate array
PLA, PLD, FPGA
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Gate array design
Two-dimensional grid of identical gates
each cell is for example a 3-input NAND gate
standard height, standard width, interleaved by routing channels
all inputs at the top, all outputs at the bottom
Cheaper:
Only the last metallisation layer is project specific
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Gate array design
Design Flow
Design entry
Map all functions to
the available 3-input
NANDs
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Contents of “Digital Design”
Introduction to the course
Data representation
Boolean algebra
Logical gates
Gates
Non-functional properties
Implementation technologies
SSI, MSI, LSI, VLSI
Custom design, standard cell design
Gate array
PLA, PLD, FPGA
1/118
Field-programmable design
Fuse programmable
One time customer programmable by selectively blowing fuses
PLA: Programmable Logic Array
PLD: Programmable Logic Device
CPLD: Complex PLD
SRAM based
FPGA: Field Programmable Gate Array (see laboratory sessions)
Properties:
Excellent for prototypes
Excellent for medium volumes (<100k pieces>For SRAM based: reconfiguration (static or dynamic) possible
2 Mgates @ 200 MHz (in 2000)
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Field-programmable design
PLA
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Field-programmable design
PLD
D
D
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Field-programmable design
CPLD
AND-OR
Plane
O
I/O
Switch matrix
I/O
O
AND-OR
Plane
AND-OR
Plane
O
I/O
I/O
AND-OR
Plane
O
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Field-programmable design
XC95216
6 Functional blocks (36V18 each)
Flash programmable
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Field-programmable design
FPGA: XC40xx
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Field-programmable design
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Field-programmable design
FPGA: Configurable Logic Block CLB
16x1
LUT:
Bool-function
of 4
variables
16x1
LUT:
Bool-function
of 4
variables
FF
G
G
GQ
FF
F
F
FQ
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Field-programmable design
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Field-programmable design
FPGA: Switching Matrix SM
Pass
TOR
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Field programmable design
Design Flow
Design entry