Data representations and computer Arithmetic

Chapter 2 :
Data representations and computer Arithmetic

2.1. Objectives
This chapter covers the most common methods that computer systems user to represent data how arithmetic operations are performed on these representations. It begins with a discussion of how integers and floating-point numbers are represented as sequences of bits.
After reading this chapter, you should
1. Have an understanding of how computers represent data internally at both the bit-pattern and the electrical-signal level
2. Be able to translate integer and floating-point numbers to and from their binary representations
3. Be able to perform basic mathematical operations (addition, subtraction, and multiplication) on integers and floating-point numbers

2.2. From Electrons to Bits (BInary digiT)
Modern computers are digital systems, meaning that they interpret electrical signals as having a set of discrete values, rather than as analog quantities. While this increases the number of signals required to convey a given of information, it makes storing information much easier and makes digital systems less subject to electrical noise than anagol systems.

2.3. Binary Representation of Positive Integers

Example
What are the binary and hexadecimal representations of the decimal number 47?

Solution
To convert decimal numbers to binary, we express them as a sum of values that are powers of two :
47 = 32 + 8 + 4 + 2 + 1 = 25 + 23 + 22 + 21 + 20
Therefore, the binary representations of 47 is 0b10111
To convert decimal numbers to hexdecimal, we can either express the number as the sumof power of 16 or group the bits in the binary representation into sets of 4 bits and look each set up in Fig.2-2. Converting directly, 47 = 2x16 + 15 = 0x2F. Grouping bits, we get 47 = 0b101111 = 0b00101111.0b0010 = 0x2,0b1111 = 0xF, so 47 = 0x2F

2.4. Arithmetic Operations on Positive Integers
EX
Compute the sum of 9 and 5 using binary numbers in 4-bit binary format
Solution
The 4-bit binary representations of 9 and 5 are 0b1001 and 0b0101, respectively. Adding the low bits, we get 0b1 + 0b1 = 0b10, which is a 0 in the low bit of the result, and a carry of 1 into the next bit position. Repeating for all bits, we get the final result of 0b1110. Figure 2-3 illustrates this process.

1 <====== Carry out of low bit of addition
0b 1 0 0 1
+ 0b 0 1 0 1
-------------------
0b 1 1 1 0

Fig. 2-3. Binary addition example


2.4.1. Addition / Subtraction
The that computers use to implement addition is very similar to the method outlined above. Modules, known as full adders, compute each bit of the output based on the corresponding bits of the input and the carry generated by the next-lower bit of computation. Figure 2-4 shows an 8-bit adder circuit.
For the type of adder described above, the speed of the circuit is determined by the time it takes for the carry signals to propagate through all of the full adders. Essentially, each full adder can not perform its part of the computation until all the full linearly with the number of bits In the inputs. Designers have developed circuits that speed this up somewhat by doing as much of the full adder as possible before the carry input is available to reduce the delay once the carry becomes available, or by taking several input bits into account when generating carries, but the basic technique remains the same.
Subtraction can be handled by similar methods, using modules that compute 1 bit of the difference between two numbers. However, the most common format for negative integers, two’s-complement notation, allows subtraction to be performed by negating the second input and subtraction. Two’s-complement notation is discussed in Section 2.5.2

2.4.2. Multiplication



2.4.3. Division
Division can be implemented on computer systems by repeatedly subtracting the divisor from the dividend and counting the number of times that the divisor can be subtracted from the dividend before the dividend becomes smaller than the divisor. For example, 15 can be dividend by 5 by subtracting 5 repeatedly from 15, getting 10, 5, and 0 as intermediate results. The quotient, 3, is the number of subtractions that had to be performed before the intermediate results became less than the dividend.
While it would be possible to build hardware to implement division through repeated subtraction, it would be impractical because of the number of subtractions required. For example, 231 (one of the larger number representable in 32-bit unsigned integers) divided by 2 is 230, meaning that 230 subtractions would have to be done to perform this division by repeated subtraction. On a system operating at 1GHz, this would take approximately 1s, far longer than any other arithmetic operation.