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COMPUTER MEMORY (DTV340)
I. INTRODUCTION – MEMORY HIERARCHY
University of Science
Faculty of Electronics and Telecommunication
Memory Description
Capacity of a memory is described as
# addresses x Word size
Endianess
Big Endian
Most significant byte of a multi-byte word is stored at the lowest memory address
e.g. Sun Sparc, PowerPC
Little Endian
Least significant byte of a multi-byte word is stored at the lowest memory address
e.g. Intel x86
Some embedded & DSP processors would support both for interoperability
Endianess
Most modern computers are byte addressable.
2
k
4
-
2
k
3
-
2
k
2
-
2
k
1
-
2
k
4
-
0
1
2
3
4
5
6
7
0
4
Byte address
(a) Big-endian assignment
Word
address

•
•
•
2
k
4
-
2
k
3
-
2
k
2
-
2
k
1
-
2
k
4
-
1
2
4
5
6
7
0
4
Byte address
(a) Little-endian assignment

•
•
•
0
3
Store
0x00010203
Memory Hierarchy
The memory unit is an essential component in any digital computer since it is needed for storing programs and data
Not all accumulated information is needed by the CPU at the same time
Therefore, it is more economical to use low-cost storage devices to serve as a backup for storing the information that is not currently used by CPU
Memory Hierarchy
Since 1980, CPU has outpaced DRAM
Memory Hierarchy

Q. How do architects address this gap?

A. Put smaller, faster “cache” memories between CPU and DRAM. Create a “memory hierarchy”.

Memory Hierarchy
The memory unit that directly communicate with CPU is called the main memory
Devices that provide backup storage are called auxiliary memory

The memory hierarchy system consists of all storage devices employed in a computer system from the slow by high-capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memory
Memory Hierarchy
The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through an I/O processor

A special very-high-speed memory called cache is used to increase the speed of processing by making current programs and data available to the CPU at a rapid rate
Memory Hierarchy
CPU
Cache
Main Memory
I/O Processor
Magnetic Disks
Memory Hierarchy
CPU logic is usually faster than main memory access time, with the result that processing speed is limited primarily by the speed of main memory
The cache is used for storing segments of programs currently being executed in the CPU and temporary data frequently needed in the present calculations
The typical access time ratio between cache and main memory is about 1 to 7~10
Auxiliary memory access time is usually 1000 times that of main memory
Types of Internal memories
Main Memory
Most of the main memory in a general purpose computer is made up of RAM integrated circuits chips

RAM– Random Access memory
Integrated RAM are available in two possible operating modes, Static and Dynamic

The Block diagram of a RAM chip is shown next slides, the capacity of the memory is 128 words of 8 bits (one byte) per word
Random-Access Memory (RAM)
Static RAM (SRAM)
Each cell stores bit with a six-transistor circuit.
Retains value indefinitely, as long as it is kept powered.
Relatively insensitive to disturbances such as electrical noise.
Faster (8-16 times faster) and more expensive (8-16 times more expensive as well) than DRAM.

Dynamic RAM (DRAM)
Each cell stores bit with a capacitor and transistor.
Value must be refreshed every 10-100 ms.
Sensitive to disturbances.
Slower and cheaper than SRAM.
RAM
ROM
ROM is used for storing programs that are PERMENTLY resident in the computer and for tables of constants that do not change in value once the production of the computer is completed
The ROM portion of main memory is needed for storing an initial program called bootstrap loader, witch is to start the computer software operating when power is turned off
ROM
Memory Model Example
32-bit address space can address up to 4GB (232) different memory locations
Memory Address Map
Memory Address Map is a pictorial representation of assigned address space for each chip in the system

To demonstrate an example, assume that a computer system needs 128 bytes of RAM and 512 bytes of ROM

The RAM have 128 byte and need seven address lines, where the ROM have 512 bytes and need 9 address lines
Memory Address Map
Memory Address Map
The hexadecimal address assigns a range of hexadecimal equivalent address for each chip

Line 8 and 9 represent four distinct binary combination to specify which RAM we chose

When line 10 is 0, CPU selects a RAM. And when it’s 1, it selects the ROM
Another Example
Making a wider memory
Here is a 64K x 16 RAM, created from two 64K x 8 chips.
The left chip contains the most significant 8 bits of the data.
The right chip contains the lower 8 bits of the data.
How to address memory
0
1
2
3
D7
D6
D5
D4
D3
D2
D1
D0
4x8 Memory
2-to-4

Decoder
CS
Chip
Select
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
0
1
2
3
D7
D6
D5
D4
D3
D2
D1
D0
4x8 Memory
2-to-4

Decoder
A0=1
A1=0
Access address = 0x1
CS
Chip
Select=1
How to address memory
Use 2 Decoders
0
1
2
3
8x4 Memory
2-to-4

Decoder

Row
Decoder
A1
A2
1-to-2 Decoder Column Decoder
D0
D1
D2
D3
0
1
CS
Chip
Select
CS
Tri-state
Buffer
(read)
A0
Tri-state Buffer
The triangle represents a three-state buffer.
Unlike regular logic gates, the output can be one of three different possibilities, as shown in the table.
“Disconnected” means no output appears at all, in which case it’s safe to connect OUT to another output signal.
The disconnected value is also sometimes called high impedance or Hi-Z.
Bi-directional Bus using Tri-state Buffer
Direction
(control data flow for read/write)
A
B
Input/Output
Read/Write Memory
0
1
2
3
8x4 Memory
2-to-4
Row
Decoder
A1
A2
1-to-2 Column Decoder
D0
D1
D2
D3
0
1
CS
Chip
Select = 0
CS
A0
Read/Write Memory
0
1
2
3
8x4 Memory
2-to-4
Row
Decoder
A1
A2
1-to-2 Column Decoder
D0
D1
D2
D3
0
1
CS
Chip
Select = 1
CS
A0